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(R)
L6353
SMART DRIVER FOR POWER MOS & IGBT
PEAK HIGH OUTPUT CURRENT CAPABILITY (+8A) WIDE SUPPLY VOLTAGE RANGE (12.5 TO 18V) 0 TO -7.5V NEGATIVE BIAS VOLTAGE SUPPLY RANGE OVER CURRENT AND DESATURATION PROTECTION OF THE EXTERNAL POWER DEVICE (EXTERNALLY PROGRAMMABLE) LATCH-UP PROTECTION (FOR IGBT) TWO STEPS TURN-ON (PROGRAMMABLE) PROTECTION AGAINST POSITIVE SUPPLY UNDER-VOLTAGE INPUT COMPATIBLE WITH OPTOCOUPLER OR PULSE TRANSFORMER PROGRAMMABLE TURN-ON DELAY THERMAL PROTECTION WITH ON-CHIP OVER-TEMPERATURE ALARM AND TURNOFF PROCEDURE OPERATING FREQUENCY UP TO 100kHz BLOCK DIAGRAM
DIP16
SO16
ORDERING NUMBERS: L6353 (DIP) L6353D (SO)
DESCRIPTION The L6353 device is a smart driver, with all the drive and protection know-how "on board". Available in both DIP and SO package, it can be triggered with a logic level or with the signal from an optocoupler or a pulse transformer. It filters parasitic input signals and drives any MOS or IGBT.
DELAY SUPPLY UV SENSE REFERENCES + - 1.25V INPUT + - FILTER 200ns THERMAL SHUTDOWN LOGIC 3.15V OUT1 CLAMPING + - VCC REF VPOS
2.5V 300A SELECT
OUT1 CLAMP_PROG OUT2
- 3.15V 1.25V INV_OUT 3.75V + - + + ALARM - 7.5V COM
D94IN106B
VSS MON_DELAY
4V ON_SENSE ON_LEV_PROG
February 2000
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L6353
DESCRIPTION (continued) It monitors the on-state voltage drop of the driven power device and protects it against overload and short circuit. The on-state voltage drop level is externally programmable from 5 to 15V. This function is inhibited during the turn-on of the external power device for an externally programmable period. An internal inhibition time of 200ns avoids false triggering. PIN CONNECTION (top view) Overload or overheating are signalled on an alarm output. If temperature continues to increase the power output is switched off and maintained in the off-state until the temperature decreases below the low threshold. A programmable turn-on delay avoids cross conduction in bridge configurations. To preserve the external power device (especially IGBT) from the risk of latch-up, the gate voltage can be risen in two different steps (of which the first is externally programmable from 7 to 11V).
OUT1 VCC VPOS CLAMP_PROG INV_OUT ALARM MON_DELAY VREF
1 2 3 4 5 6 7 8
D94IN113A
16 15 14 13 12 11 10 9
OUT2 COM VSS ON_SENSE ON_LEV_PROG SELECT DELAY INPUT
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VSS
VPOS - VOUT1
Parameter Supply Voltage referred to COM pin Negative Supply Voltage referred to COM pin Collector-Emitter Voltage of High Side NPN Drain-Source Voltage of Low Side DMOS Externally Forced Voltage (pin 9) Externally Forced Voltage (pins 4,7,10, 11, 12) Sink Current pin Delay Sink Current Pin Mon_Delay Voltage on ON_SENSE Pin Positive Output Current (tp 1ms) (peak) Negative Output Current (tp 1ms) (peak) Output Current in INV_OUT Pin Output Current in ALARM Pin Total Power Dissipation Operating Temperature Range Storage Temperature
Value 20 - 8 to 0 25 25 -0.3 to VCC -0.3 to 7 3 3 VSS-0.3 to VCC 8 8 20 20 internally limited -25 to +85 -50 to +150
Unit V V V V V V mA mA V A A mA mA C C
VOUT2 - VSS VEXT1 VEXT2 IDELAY IMON_DELAY VON_SENSE IOUT1 IOUT2 IINV_OUT IALARM Ptot Tamb Tstg
THERMAL DATA
Symbol Rthj-ambient Parameter Thermal Resistance Junction-ambient Max DIP16 80 SO16 90 Unit C/W
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L6353
PIN FUNCTIONS
N. 1 2 3 4 Name OUT1 VCC VPOS CLAMP_PROG Function Output of high side driver (emitter of power NPN transistor). Positive Supply Voltage (referred to COM). See under voltage lockout functioning Positive Bias Voltage (collector of the NPN power transistor). First Step of the Gate Voltage Programming. The programming is achieved setting an appropriate voltage on this pin (i.e. using a resistence voltage divider). Inverted Output Driver Status. The buffer output is able to drive some auxiliary circuit (i.e. a LED). Diagnostic Output Signal. A fault condition is signalled by this output buffer. VON Monitor Delay. An R-C network connected between this, the COM and the V REF pins, define tMON_DELAY time interval (see fig 4) Output of the 5V/10mA internal voltage reference. Input signal. The driving signal can be a logic level either active LOW (inverted mode) or HIGH (direct mode) in the Logic Level or a pulse in the Pulse Transformer Mode (see Figure 2) On Triggering Delay. An R-C network connected between this, the COM and the VREF pins, definethe tDELAY time interval (see fig 4) Select the direct/inverted mode in the Logic Level Mode. It's also the reference pin in Pulse transformer mode. VON level programming. This pin is used to set the VON monitor level. The programming is achieved setting an appropriate voltage on this pin (i.e. using a resistive divider). On State Monitor. This pin is used to monitor the turning on of the external power device. Negative supply voltage (referred to the COM). This pin is the source of the low side driver DMOS. Ground Output of the low side driver (drain of the DMOS).
5 6 7 8 9
INV-OUT ALARM MON_DELAY VREF INPUT
10 11 12
DELAY SELECT ON_LEV_PROG
13 14 15 16
ON_SENSE VSS COM OUT2
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L6353
DC ELECTRICAL CHARACTERISTICS (VPOS = VCC=15V; VSS = -5 to 0V; Tj = -25 to +125C; unless otherwise specified)
Symbol Vdrop VCC VCCth1 VCCth2 VCChys ICCq Vd Iso Isi Vdrop_sig Vref R in Vdth R ins Iouts VSS R ON Vil Vih Iin tinh Vton Vtoff Vsl Vsh Isl Vsel 11 14 16 9 13 5, 6 8 7, 10 4, 12 Pin 1 2 Parameter VPOS - VOUT1 Operating Supply Voltage Under Voltage Upper Threshold Under Voltage Lower Threshold Under Voltage Hysteresis Quiescent Supply Current Output Voltage Sourced Current Sinked Current Low State Output Voltage Drop Output of Internal Voltage Reference Comparator Input Resistance Comparator Threshold Input Resistance Output Current Operating Negative Bias Voltage On Resistance Low Level Voltage High Level Voltage Input Current Inhibited Parasitic Pulse Duration Turn-on Threshold Voltage Turn-off Threshold Voltage Low Level Voltage High Level Voltage Current Output of SELECT Pin Output Voltage of SELECT Pin pin grounded (referred to COM) OUT2 to VSS); IOUT2 = 2A (Logic Level Mode) (Logic Level Mode) 0High State Output Voltage Drop Iout = 20mA
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L6353
AC ELECTRICAL CHARACTERISTICS
Symbol ton toff tr tf tfault Pin 9 vs 1 Parameter Turn on Propagation Delay Time Test Condition Min. Typ. 400 400 50 50 400 Max. Unit ns ns ns ns ns
9 vs 16 Turn off propagation delay time 1,16 Rise Time Fall Time Delay Time for Fault Detection
THERMAL PROTECTION
Symbol Tth1 Thys1 Tth2 Thys2 Parameter Over Temperature Threshold Over Temperature Threshold Hysteresis Over Temperature Shutdown Over Temperature Shutdown Hysteresis Test Condition (Thermal Procedure) Min. Typ. 130 20 160 20 Max. Unit C C C C
Figure 1: Switching waveforms and test circuit
V in 5V 50% 50%
0 tW tON VOUT 90% 50% 10% tr tf 90% 50% 10%
D94IN107
t tOFF
t
Figure 1a : Switching waveforms and test circuit
POSITIVE SUPPLY 100F SELECT VREF INPUT 100nF 100nF NEGATIVE SUPPLY 100F V CC 11 8 9 2 VPOS 3 13 VON_SENSE
1
OUT1 OUT2 1nF COM
D.U.T.
16
Vin VSS 14 4 MON_ DELAY 4.7K 7 DELAY 4.7K VREF 10 15
VCLAMP_ PROG
D94IN108B
VREF
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L6353
Figure 2. Pulse Transformer mode operation.
Vin tW V ton = Vsel +1.5V INPUT Vsel Vin SELECT INPUT PULSE TRANSFORMER
D94IN114
tW
V toff = Vsel -1.5V
ON
OFF
t
Figure 3. Gate driving voltage waveforms.
Vin
t VOUT1 VPOS VCL
VSS tDELAY VG VPOS VCL VMILLER VSS
t
t MILLER =
Q GATE R G' V CL - V MILLER
QGATE (device dependent) defined between 0V and VCL
tMON_DELAY tMILLER t
trr VCE/VDS VH.V. tr
Short circuit or overcurrent protected area
VONth
D94IN115
t
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L6353
Figure 4. Gate driving waveforms test circuit.
VH.V. POSITIVE SUPPLY 100F-35V VCC SELECT 100nF OUT1 LOGIC OUT2 Vin VREF 100nF CLAMP_PROG MON DELAY 100nF (*) 47K VREF DELAY ON_LEV_PROG COM 5.6 1.2 VG V POS ON_SENSE DFW LOAD
INPUT
VCE
VSS (**) 100F-10V
NEGATIVE SUPPLY
1nF 4.7K V REF
100pF 12K VREF 12K
100nF (*)
D94IN116B
12K VREF
2.2K
NOTES: (*) The capacitor is required if the pin is left floating. (**) If the negative supply is not used, the VSS pin must be connected to the COM pin as close as possible to the IC.
INPUT INTERFACE To drive the external power device three different possibilities are allowed: The Logic Level Mode, either direct or inverted, and the Pulse Transformer Mode Using the Logic Level Mode (direct) an high level (referred to COM), at the INPUT pin will start the Turn on Procedure (i.e. firing an N channel external device). A low level (referred to COM) will instead close the OUT2 pin to VSS. The functioning is reversed in the inverted mode. To select the direct mode the SELECT pin must be connected via a capacitor to COM. The inverted mode is chosen by connecting the SELECT pin to COM. In logic Level Mode pulses lasting less than t inh (200ns typ.) are filtered out. In the Pulse Transformer Mode the SELECT pin will be the reference pin for the signal applied to the INPUTpin. The positive pulse will start the TURN ON PROCEDURE, while the negative pulse will close OUT2 to VSS. The duration of this pulses (tw, see fig.2) must be again tw > tinh. TURN-ON PROCEDURE The firing of the external power device is performed in three steps in order to avoid the most common problems that can arise. In each of these steps there are a number of parameters that can be easily externally presetted to
the requested values. First Step Parameter: tDELAY In order to avoid cross-conduction between the external power device in half bridge arrangement the driver output is activated after an externally programmable delay time (tDELAY, see fig. 3) after the input signal. To set the tDELAYinterval an R-C network has to be connected between the DELAY, VREF and COM pins (see fig.4) giving: tDELAY (sec) = REXT (K) . CEXT(nF)+ t on To minimize this interval only a resistor has to be connected between the DELAY and the VREF limiting thus the duration to the internal propagation delay ton. Second step Parameters: tMON_DELAY, VCL To protect the driven device from latch-up at turnon (IGBT) after the t DELAY time interval a second externally programmable time interval tMON_DELAY (presettable using the same technique used to set the tDELAY interval, see fig.4) tMON-DELAY (sec) = REXT (K) . CEXT(nF) during the tMON_DELAY the voltage on the VOUT1) is limited to the VCL level. To program this value an appropriate voltage drop has to be imposed, by mean of a resistive voltage divider, at the CLAMP_PROG pin according to the following formula:
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L6353
VCLAMP_PROG = with VCL 6 level is set to 7.5V. The overload status is signalled via the ALARM pin, active LOW. To inhibite the VON Monitor function, the VSENSE pins must be grounded. THERMAL PROCEDURE As the junction temperature raises, two different events will take place. When the Over Temperature Threshold (Tth1), set at 130C is reached, the ALARM output is activated (low level). If the temperature keeps on raising, up to the Over Temperatur Shutdown (Tth2 = 160C Typ) the output power device is turned off until the temperature decrease. To prevent an oscillating behaviour both the thresholds have a built-in hysteresis of 20C. UNDERVOLTAGE LOCK OUT To avoid operation with non optimal drive of the external power device, an Undervoltage Lockout function is implemented. The OUT1 pin is forced close to VSS until the VCC supply voltage has reached the Undervoltage Upper Threshold (VCCth2) value. If the supply voltage falls below the lower hysteresis value (i.e. VCCth1 - VCChys) the OUT1 will be again forced close to VSS. The built-in hysteresis will thus avoid intermittent functioning of the device at low supply voltage that may have a superimposed ripple.
7V < VCL <11V Leaving the CLAMP_PROG pin floating the VCL level is set to 9V. If the pin is grounded the function is inhibited (i.e. no intermediate step during the firing). Third step Parameter: VONth At the end of the tMON_DELAY the gate of the driven device is pulled toward the VPOS level in order to ensure an appropriate drive to minimize the power losses. The external power device is considered in overload whenever the voltage on its output, sensed via the VON_SENSE pin, is above VONth. The comparison value is programmable setting at a certain level, by means of a resistive divider, the ON_LEV_PROG pin according to the following formula: VON_LEV_PROG = VONth. 0.17 with 5V < VONth. < 15V and VONth. < VCC -1V. If the ON_LEV_PROG pin is left floating theVONth. Undervoltage Comparator Hysteresis
Vcchys
Vccth
D94IN126B
Vs
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L6353
DIM. MIN. a1 B b b1 D E e e3 F I L Z 0.51 0.77
mm TYP. MAX. MIN. 0.020 1.65 0.5 0.25 20 8.5 2.54 17.78 7.1 5.1 3.3 1.27 0.030
inch TYP. MAX.
OUTLINE AND MECHANICAL DATA
0.065 0.020 0.010 0.787 0.335 0.100 0.700 0.280 0.201 0.130 0.050
DIP16
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L6353
mm MIN. A a1 a2 b b1 C c1 D (1) E e e3 F (1) G L M S 3.8 4.6 0.4 9.8 5.8 1.27 8.89 4 5.3 1.27 0.62 8(max.) 0.150 0.181 0.016 0.35 0.19 0.5 45 (typ.) 10 6.2 0.386 0.228 0.050 0.350 0.157 0.209 0.050 0.024 0.394 0.244 0.1 TYP. MAX. 1.75 0.25 1.6 0.46 0.25 0.014 0.007 0.020 0.004 MIN. inch TYP. MAX. 0.069 0.009 0.063 0.018 0.010
DIM.
OUTLINE AND MECHANICAL DATA
SO16 Narrow
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
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L6353
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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